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MOSEL VITELIC
V53C832L HIGH PERFORMANCE 3.3 VOLT 256K X 32 EDO PAGE MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
30
30 ns 16 ns 12 ns 65 ns
35
35 ns 18 ns 14 ns 70 ns
40
40 ns 20 ns 15 ns 75 ns
Features
s 256K x 32-bit organization s EDO Page Mode for a sustained data rate of 83 MHz s RAS access time: 30, 35, 40 ns s Four CAS Inputs for Byte Read and Byte Write Control s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Refresh Interval: 512 cycles/8 ms s Available in 100-pin PQFP and 100-pin LQFP packages s Single +3.3V 0.3V Power Supply s TTL Interface
Description
The V53C832L is a high speed 262,144 x 32 bit high performance CMOS dynamic random access memory. The V53C832L offers a combination of unique features including: EDO Page Mode operation for higher sustained bandwidth with Page Mode cycle times as short as 12ns. All inputs are TTL compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features make the V53C832L ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range 0C to 70C Package Outline Q * TQ * 30 * Access Time (ns) 35 * 40 * Power Std. * Blank Temperature Mark
V53C832L Rev. 1.6 August 1999
1
MOSEL VITELIC
V 5 3 C 8 3 2 L
V53C832L
FAMILY
DEVICE Q (PQFP) TQ (TQFP)
PKG
Description PQFP TQFP
Pkg. Q TQ
Pin Count 100 100
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL)
30 (30 ns) 35 (35 ns) 40 (40 ns)
832L-01
100-Pin PQFP/TQFP PIN CONFIGURATION Top View
I/O3 VSS I/O2 I/O1 VCC NC NC NC NC NC NC NC NC NC NC VSS I/O32 I/O31 VSS I/O30
Pin Table
A0-A8 RAS CAS0 CAS1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O29 VCC I/O28 I/O27 VSS I/O26 I/O25 VCC I/O16 I/O15 VSS I/O14 I/O13 VCC VSS VCC I/O12 I/O11 VSS I/O10 I/O9 VCC NC CAS3 CAS1 NC NC OE NC A8
Address Inputs Row Address Strobe Column Address Strobe for First Byte (I/O1-I/O8) Column Address Strobe for Second Byte (I/O9-I/O16) Column Address Strobe for Third Byte (I/O17-I/O24) Column Address Strobe for Fourth Byte (I/O25-I/O32) Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect
I/O4 VCC I/O5 I/O6 VSS I/O7 I/O8 VCC I/O17 I/O18 VSS I/O19 I/O20 VCC VCC VSS I/O21 I/O22 VSS I/O23 I/O24 VCC CAS0 CAS2 WE NC NC RAS NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
CAS2 CAS3 WE OE I/O1-I/O32 VCC VSS NC
A0 A1 A2 A3 VCC NC NC NC NC NC NC NC NC NC NC VSS A4 A5 A6 A7
832H-02
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature Under Bias ................................. -10C to +80C Storage Temperature (plastic) ..... -55C to +125C Voltage Relative to VSS ..................-1.0 V to +4.6V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C832L
Capacitance*
Symbol
CIN1 CIN2 COUT
TA = 25C, VCC = 3.3V 0.3V, VSS = 0 V
Parameter
Address Input RAS, CAS, WE, OE Data Input/Output
Typ.
3 4 5
Max.
4 5 7
Unit
pF pF pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
256K x 32
OE WE CAS0 CAS1 CAS2 CAS3 RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32
832L-03
DATA I/O BUS COLUMN DECODERS
Y0 -Y8
SENSE AMPLIFIERS
512 x 32
REFRESH COUNTER
9 A0 A1
I/O BUFFER
ADDRESS BUFFERS AND PREDECODERS
X0 -X 8
ROW DECODERS
512
* * *
A7 A8
MEMORY ARRAY 512 x 512 x 32
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC = 3.3V 0.3V, VSS = 0 V, unless otherwise specified.
V53C832L Symbol
ILI ILO ICC1
V53C832L
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Time
Min.
-10
Typ.
Max.
10
Unit
A A mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
30 35 40
130 120 110 4
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 30 35 40
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
130 120 110 120 110 100 2.0
mA
ICC4
VCC Supply Current, EDO Page Mode Operation
30 35 40
mA
Minimum Cycle
1, 2
ICC5 ICC6
VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby
mA
RAS=VIH, CAS=VIL RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS
1
2.0
mA
VCC VIL VIH VOL VOH
Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
3.0 -1 2.4
3.3
3.6 0.8 VCC+1 0.4
V V V V V IOL = 2 mA IOH = -2 mA 3 3
2.4
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
TA = 0C to 70C, VCC = 3.3V 0.3V, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
30 #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V53C832L
AC Characteristics
35
40 Notes
Symbol
tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH tWP tWCR tRWL tDS tDH RAS Pulse Width
Parameter
Min. Max. Min. Max. Min. Max. Unit
30 65 25 30 5 15 0 0 5 0 5 10 5 0 20 75K 35 70 25 35 6 16 0 0 6 0 5 10 5 0 24 75K 40 75 25 40 7 17 0 0 7 0 5 10 5 0 28 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time fromRAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time
4
5
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
0 6 10 10 30 16 0 0 26 10 10 10 0 5 5 26 10 0 5 14 5
0 7 11 11 35 18 0 0 28 11 10 11 0 5 5 28 11 0 5 17 6
0 8 12 12 40 20 0 0 30 12 10 12 0 5 5 30 12 0 5 20 6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
12 6,7,14 6, 8, 9 6,7,10 16 16
11
12, 13
14 14
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
AC Characteristics (Cont'd)
30 #
34 35 36 37
V53C832L
35
40 Notes
14 14
Symbol
tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tCOH tOES tOEH tOEP tT tREF
Parameter
Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay EDO Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS- before-RASRefresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh EDO Page Mode Read-Modify-Write Cycle Time Output Hold After CAS Low OE Low to CAS HIGH setup time OE Hold Time from WE during Read-Modify Write Cycle OE High Pulse Width Transition Time (Rise and Fall) Refresh Interval (512 Cycles)
Min. Max. Min. Max. Min. Max. Unit
5 5 100 65 5 5 105 70 6 6 110 75 ns ns ns ns
38 39
26 50
28 54
30 58
ns ns
12 12
40 41 42
44 32 12
46 35 14
48 38 15
ns ns ns 12
43 44 45 46 47 48 49 50 51 52 53
3 16 19 26 10 0 7 56 5 5 10
4 18 21 28 10 0 8 58 5 5 10
5 20 23 30 10 0 8 60 5 5 10
ns ns ns ns ns ns ns ns ns ns ns 7
54 55 56
10 1.5 50 8
10 1.5 50 8
10 1.5 50 8
ns ns ms 15 17
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
Notes:
V53C832L
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL inputs and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C832L Rev. 1.6 August 1999
7
MOSEL VITELIC
Truth Table
Function
Standby Read: Double Word Read: First Byte Read: Second Byte
V53C832L
RAS
H L L L
CAS0 CAS1 CAS2 CAS3 WE
H L L H H L H L H L H H H L H H X H H H
OE
X L L L
ADDRESS I/O
X ROW/COL ROW/COL ROW/COL High-Z Data Out I/O1-I/O8 = Data Out I/O9-I/O32 = High-Z I/O1-I/O8 = High-Z I/O9-I/O16 = Data Out I/O17-I/O32 = High-Z I/O1-I/O16 = High-Z I/O17-I/O23 = Data Out I/O24-I/O32 = High-Z I/O1-I/O23 = High-Z I/O24-I/O32 = Data Out Data In I/O1-I/O8 = Data In I/O9-I/O32 = X I/O1-I/O8 = X I/O9-I/O16 = Data In I/O17-I/O32 = X I/O1-I/O16 = X I/O17-I/O23 = Data In I/O24-I/O32 = X I/O1-I/O23 = X I/O24-I/O32 = Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In
Notes
Read: Third Byte
L
H
H
L
H
H
L
ROW/COL
Read: Fourth Byte Write: Double Word (Early-Write) Write: First Byte (Early) Write: Second Byte (Early) Write: Third Byte (Early) Write: Fourth Byte (Early) Read-Write EDO Page-Mode Read First Cycle EDO Page-Mode Read Subsequent Cycles EDO Page-Mode Write First Cycle EDO Page-Mode Write Subsequent Cycles EDO Page-Mode Read-Write First Cycles EDO Page-Mode Read-Write Subsequent Cycles Hidden Refresh Read RAS-Only Refresh CBR Refresh
L L L L
H L L H
H L H L
H L H H
L L H H
H L L L
L X X X
ROW/COL ROW/COL ROW/COL ROW/COL
L
H
H
L
H
L
X
ROW/COL
L L L L L L L
H L HL HL HL HL HL
H L HL HL HL HL HL
H L HL HL HL HL HL
L L HL HL HL HL HL
L HL H H L L HL
X
ROW/COL
LH ROW/COL L L X X ROW/COL COL ROW/COL COL
1,2 2 2 2 2 2
LH ROW/COL
L
HL
HL
HL
HL
HL
LH COL
Data Out, Data In
2
LHL L HL
L H L
L H L
L H L
L H L
H X X
L X X
ROW/COL ROW X
Data-Out High-Z High-Z
2
3
Notes:
1. Byte Write cycles CAS0, CAS1, CAS2, or CAS3 active. 2. Byte Read cycles CAS0, CAS1, CAS2, or CAS3 active. 3. Only one of the four CAS (CAS0, CAS1, CAS2, or CAS3) must be active.
V53C832L Rev. 1.6 August 1999
8
MOSEL VITELIC
Waveforms of Read Cycle
t RAS (1) t RC (2) t RP (3)
V53C832L
RAS
VIH VIL t CRP (13)
t AR (23)
t RCD (6) t RAD (24)
t CSH (4)
CAS CAS0-CAS3
VIH VIL t ASR (8) t RAH (9)
t RSH (R)(12) t CAS (5)
t CRP (13)
t ASC (10)
t CAH (11)
ADDRESS
VIH VIL
ROW ADDRESS
COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15)
t RCS (7) WE VIH VIL
t ROH (16) t CAA (20) t OAC (17) t OES (52)
OE
VIH VIL
I/O1-I/O32
VOH VOL
t RAC (19)
t CAC (18)
t HZ (22) VALID DATA-OUT
t HZ (22)
t LZ (21)
832L-04
Waveforms of Early Write Cycle
t RC (2) t RAS (1) RAS V IH V IL t CSH (4) t CRP (13) CAS0-CAS3 V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t RAD (24) t ASC (10) COLUMN ADDRESS t WCH (28) t CAR (44) t CAH (11) t RCD (6) t RSH (W)(25) t CAS (5) t CRP (13) t AR (23) t RP (3)
t CWL (26) t WP (29) t WCS (27)
WE
V IH V IL
t WCR (30) t RWL (31) OE V IH V IL t DHR (46) t DS (32) I/O1-I/O32 V IH V IL t DH (33) VALID DATA-IN HIGH-Z
832L-05
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
9
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RAS (1) t RC (2) t RP (3)
V53C832L
RAS
V IH V IL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS0-CAS3
V IH V IL t RAD (24) t RAH (9)
t RSH (W)(12) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
t ASR (8) ADDRESS V IH V IL
ROW ADDRESS
COLUMN ADDRESS t CWL (26) t RWL (31)
t WP (29) WE V IH V IL
t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN
832L-06
I/O1-I/O32
Waveforms of Read-Modify-Write Cycle
t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) CAS CAS0-CAS3 VIH VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t ACS VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O1-I/O32 VIH VIL VOH VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN
832L-07
t RP (3)
t AR (23)
t RCD (6)
t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26)
t CRP (13)
CAH (11)
t RWD (39)
t WP (29)
WE
t CAA (20) t OAC (17) t OEH (53) t DH (33)
OE
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
10
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
RAS V IH V IL t AR (23) t RCD (6) t CRP (13) CAS0-CAS3 V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) t RCS (7) t CAR (44) t CAH (11) COLUMN ADDRESS t RCS (7) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t CRP (13) t CAS (5) t RAS (1) t
V53C832L
RP (3)
t CAS (5)
t ASR (8) ADDRESS V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
COLUMN ADDRESS
t RCH (14)
WE
V IH V IL t CAP (45) t OES (52) t OEP (54) t CAC (18) t CAA (20) t OAC (17) t RRH (15)
t CAC (18) t COH (5)
t HZ (22) t HZ (22) t HZ (22) VALID DATA OUT
t HZ (22) VALID DATA OUT t LZ
I/O1-I/O32
V OH V OL
VALID DATA OUT
832L-08
Waveforms of EDO Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) CAS0-CAS3 V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32)
I/O1-I/O32
ROW ADD COLUMN ADDRESS
t RP (3) t RAS (1)
t PC (42) t CP (43) t CAS (5)
t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
OE
t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
V IH V IL
OPEN
OPEN
832L-09
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
11
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
RAS VIH V
IL
V53C832L
t RAS (1)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V CAS0-CAS3 V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RWD (39) t CWD (38) V WE V
IH IL
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17) t OEH (53) t CAA (20) t CAP (43)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32)
I/O1-I/O32
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN
832L-10
V I/OH V I/OL t LZ (21)
OUT
IN
OUT
IN
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
tRC (2) VIH V IL t CRP (13) VIH V IL tASR (8) t RAH (9) VIH V IL t RAS (1) tRP (3)
RAS
CAS0-CAS3
ADDRESS
ROW ADD
832L-11
NOTE: WE, OE = Don't care
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
12
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS V IH V IL t CSR (47) t CHR (49) t CP (43) t RSH (W)(25) t CAS (5)
V53C832L
t RP (3)
CAS0-CAS3
V IH V IL V IH V IL READ CYCLE t RRH (15) t RCH (14)
ADDRESS
t RCS (7)
WE
V IH V IL t ROH (16) t OAC (17)
OE
V IH V IL t LZ (21) t HZ (22) t HZ (22) DOUT t RWL (31) t CWL (26) t WCS (27) t WCH (28)
I/O1-I/O32
V IH V IL WRITE CYCLE
WE
V IH V IL V IH V IL t
DS (32)
OE
t DH (33) D IN
832L-12
I/O1-I/O32
V IH V IL
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22)
I/O1-I/O32
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS0-CAS3
V OH V OL NOTE: WE, OE, A0-A8 = Don't care
832L-13
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
13
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS0-CAS3 V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) t OAC (17) OE V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O1-I/O32 V OH V OL VALID DATA t HZ (22) t HZ (22)
ROW ADD
V53C832L
t RC (2) tRP (3) t RAS (1) t RP (3)
t RAS (1) t AR (23)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
t RCS (7) WE
t RRH (15)
832L-14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH V IL t RCD (6) t CRP (13) t RSH (12) t CHR (49) t CRP (13) t RAS (1) t AR (23) t RP (3) t RAS (1) t RC (2) t RP (3)
RAS
CAS0-CAS3
V IH V IL t ASR (8) t RAH (9) t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
ADDRESS
V IH V IL V IH V IL V IH V IL
ROW ADD
t WCS (27) WE
t WCH (28)
OE
t DS (32)
t DH (33)
VALID DATA-IN
I/O1-I/O32
V IH V IL
t DHR (46)
832L-15
Don't Care
V53C832L Rev. 1.6 August 1999
Undefined
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MOSEL VITELIC
V53C832L
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRAS V IH RAS V IL tCSH tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tCAR tRCD tPC tCAS tCP tCAS tPC tCP tRSH tCAS tCP tRP
CAS0-CAS3
ADDRESS
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRCS V IH WE V IL tRAC tCAC V IH V IL
tRCH tWCS tWCH
tCAA tCAP
tCAA
tCAC
tDS
tDH
OE
tOE tCOH
I/O1-I/O32
VOH VOL
VALID DATA OUT
VALID DATA OUT
VALID DATA IN 832L-16
Don't Care
Undefined
Functional Description
The V53C832L is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C832L reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The V53C832L has four CAS inputs. CAS0 controls I/O1-I/O8; CAS1 controls I/O9-I/O16; CAS2 controls I/O 17 -I/O 24 ; and CAS3 controls I/O 23 - I/O 32 . These four CAS inputs control Byte Read and Byte Write. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
Extended Data Output Page Mode EDO Page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-WriteRead cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 83 MHz for applications that require high bandwidth such as bitmapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate:
512 Data Rate = ---------------------------------------t RC + 511 x t PC
V53C832L
OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
Power-On After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C832L is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
Table 1. V53C832L Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-Modify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
Data Output Operation
The V53C832L Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The
V53C832L Rev. 1.6 August 1999
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MOSEL VITELIC
Package Outlines
100-pin PQFP
FOOTPRINT 3.2mm (14x20mm) 0.026 TYP. [0.65 TYP.] 100 1 80
V53C832L
TOP VIEW
81
0.134 MAX. [3.404 MAX.] 0.010 MIN. [0.254 MIN.]
Unit in inches [mm]
0.7870.004 [19.9900.102]
0.012
+0.003 -0.002
[0.305
+0.076 ] -0.051
+0.008 -0.007 +0.203 [23.190 ] -0.178 0.913
30
51
31 0.5510.004 [13.9950.102] 0.6770.008 [17.1950.203]
50 0.113 MAX [2.87 MAX]
DETAIL "F" 0.004 MIN. [0.102 MIN.] GAGE PLANE 0.035 0.006 [0.889 0.152] 0.063 TYP. [1.600 TYP.]
SEATING PLANE
SEE DETAIL "F"
100-pin TQFP
Dimensions in Millimeters
17.2 Pin #1 Index #100 #1
0.25 0.20
14.00
23.2
0.25
20.00 A A
0.20
0.30
0.08
0.65
0.15
0.05
1.00
0.05
1.20 MAX
GAGE PLANE 0.10 0.05 1.60
REF
0.80
0.15
SECTION: A-A
V53C832L Rev. 1.6 August 1999
17
MOSEL VITELIC
U.S.A.
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WORLDWIDE OFFICES
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V53C832L
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71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
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NORTHEASTERN
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(c) Copyright 1998, MOSEL VITELIC Inc.
8/99 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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